1. Field of the Invention
The present invention relates generally to a semiconductor memory device. More specifically, the invention relates to a layout structure of a DARM cell array using a trench capacitor.
2. Description of the Related Background Art
FIG. 28 shows an example of a conventional layout of a DRAM cell array using trench capacitors. On a semiconductor substrate, elongated island active regions 1 are arranged and formed, and trench capacitors 2 are formed on both ends of each of the active regions 1. In each of the active regions 1, there are formed transistors 3, each of which is associated with a corresponding one of the trench capacitors 2 on both sides to constitute a memory cell. The gate electrodes of the transistors 3 are continuously arranged in column directions as word lines WL. The source or drain diffusion layers of the transistors 3 arranged in row directions are connected to bit lines BL, and the drain or source diffusion layers of the transistors 3 are connected to corresponding trench capacitors 2.
The example of FIG. 28 is arranged and formed so that the active regions 1 have a width of 6F and a space of 2F between adjacent two thereof in the row directions and have a width of 1F and a space of 1F between adjacent two thereof in the column directions, assuming that the minimum working dimension is F. Both of the word lines WL and bit lines BL are formed so that line/space=1F/1F. Therefore, the area occupied by a unit memory cell shown by a chain line in the figure is 4F.times.2F=8F.sup.2. The memory cell having this layout will be hereinafter referred to as a "8F.sup.2 cell".
In DRAM cell arrays of this type, there are two systems for connecting the diffusion layers of the transistors 3 to the trench capacitors 2. As shown in FIG. 29, one of the systems utilizes a lateral diffusion layer 5 of the impurity of a capacitor node layer 4 of the trench capacitor 2 toward the active region 1. By the lateral diffusion layer 5, the diffusion layer of the transistor 3 is connected to the capacitor node layer 4 in the substrate. This system will be hereinafter referred to as a "buried strap system" As shown in FIG. 30, the other system is a system for connecting the capacitor node layer 4 of the trench capacitor 2 to the diffusion layer of the transistor 3 by means of a connecting conductor 6 formed on the substrate. This system will be hereinafter referred to as a "surface strap system".
FIG. 31 shows a layout of a DRAM cell array scaled down as compared with the 8F.sup.2 cell of FIG. 28. In this layout, the elongated island active regions 1 are formed so as to have a width of 4F and a space of 1F between adjacent two thereof in the row directions to be divided into smaller regions than those of FIG. 28. The size of a unit memory cell is 3F.times.2F=6 as shown by a dashed line in the figure. Therefore, the memory cell having this layout will be hereinafter referred to as a "6F.sup.2 cell". In this layout of the 6F.sup.2 cell, the bit lines BL are provided so as to be inclined with respect to row directions so that the sense amplifier system is a folded bit line system. If the bit lines are provided so as to extend in directions perpendicular to the word lines WL similar to FIG. 28, two memory cells driven by one word line are connected to adjacent bit lines, so that it is not usually possible to adopt the folded bit line structure.
Although the 6F.sup.2 cell shown in FIG. 31 is scaled down as compared with the 8F.sup.2 cell shown in FIG. 28, there are the following disadvantages by the scale down.
(1) The area occupied by the trench capacitor 2 is about 1.5F.times.1F which is smaller than that of the 8F.sup.2 cell. It is not possible to ensure a smaller capacitor area than this since insulation failure occurs between adjacent active regions and/or since it is difficult to connect the capacitor to the transistor. Therefore, it is difficult to ensure a sufficient capacity of a capacitor.
(2) The distance between the trench capacitor 2 and the transistor 3 is small. Therefore, if either of the buried strap system or the surface strap system is used, it is difficult to surely connect the trench capacitor 2 to the diffusion layer of the transistor 3. For example, if the buried strap system is used, there is a disadvantage in that the lateral diffusion layer 5 of the impurity from the capacitor node layer 4 extends to the channel region of the transistor. This damages the normal operation of the transistor. In addition, if the surface strap system is used, it is not possible to sufficiently ensure the contact area of the connecting conductor 6 for connecting the capacitor 2 to the transistor 3. Moreover, if the surface strap system is used, generally, when the connecting conductor 6 is patterned, it is required to perform precise alignment between the word lines WL and the trench capacitors 2 in a lithography process. If the alignment is offset, it is not possible to surely connect the trench capacitor 2 to the diffusion layer of the transistor.
(3) In order to adopt the folded bit line system, it is required to cause the bit lines BL to incline as shown in FIG. 31. In this case, as can be clearly seen from the figure, the space between adjacent bit lines BL is less than 1F. Therefore, the bit lines BL must be formed in two layers.